1. Field of the Invention
The present invention relates to semiconductor memory devices, and, more particularly, to a dynamic random access memory having a stacked capacitor cell structure.
2. Description of the Related Art
With the increasing needs for high performance of digital systems, developments of semiconductor memory devices, particularly, random access memories, continue for higher integration density. With restriction on the size of a chip substrate, if many memory cells, each constituted by one transistor and one capacitor, are simply packed, the occupying area of each memory cell would decrease The reduction of the memory cell size decreases the area of the cell capacitor. This deteriorates the performance of accumulating data charges. For instance, reduction in electrode area of a capacitor decreases the maximum amount of charge accumulatable, thus resulting in malreading of memory contents and increasing the chance of causing data damage by radiation. This impairs the reliability of data accessing accordingly.
Recently, for a dynamic random access memory (hereinafter called "DRAM" according to the practice of the concerned technical field), it becomes popular to employ the "stacked capacitor cell" structure in order to pack a greater number of memory cells on a chip substrate with a limited size without reducing the reliability of data accessing. According to this technique, a capacitor is insulatively disposed above a cell transistor formed on the chip substrate. An insulative layer sandwiched between the transistor and capacitor has a contact hole formed therein. An electrode of the capacitor is electrically coupled via the hole to the diffusion layer of the underlying transistor, which serves as a source or drain thereof.
The integration of DRAMS is generally improved by effectively increasing the effective area of a cell capacitor electrode to thereby increase the capacitance of the capacitor. According to DRAMS with the aforementioned stacked capacitor cell structure, however, higher integration of the DRAMs employing such a technique cannot be expected for the following reasons To increase the effective area of the capacitor electrode without increasing the occupying area of each capacitor on the substrate, a recess should be formed in an insulative layer for electrically separating the transistor from capacitor and the lower electrode layer of the cell capacitor should be formed so as to be stuck to the inner wall of the recess. The higher the integration density of DRAMs, the smaller the area of one cell becomes and, naturally, the narrower the recess gets. With the present state-of-art technology, therefore, it is very difficult to effectively form, within the recess, a capacitor electrode layer, which is expected to be relatively thick to have a thickness greater than a predetermined value. If the electrode layer portions formed on the facing inner walls of the recess come in contact with each other, the entire effective area of the capacitor electrode cannot be increased.